`timescale 1 ns/10 ps
module tb_fulladd;
wire sum,c_out;
reg a,b,c_in;

fulladd  fadd(a,b,c_in,c_out,sum);

initial
begin
        a=0;b=0;c_in=0;
    #1000 a=0;b=0;c_in=1;
    #1000 a=0;b=1;c_in=0;
    #1000 a=0;b=1;c_in=1;
    #1000 a=1;b=0;c_in=0;
    #1000 a=1;b=0;c_in=1;
    #1000 a=1;b=1;c_in=0;
    #1000 a=1;b=1;c_in=1;
    #1000 $stop;
end
endmodule